The present invention relates to a sense amplifier circuit, and more particularly to a latch sense amplifier circuit to be used in a semiconductor memory device.
Recently, due to increases in the requirement for improvements in high speed performances of semiconductor devices and for possible reduction in power consumption of semiconductor devices, semiconductor memory devices are also requited to have improved high speed performance and reduced power consumption.
There are known different types of the sense amplifier circuits, wherein a latch type sense amplifier circuit is advantageous for zero stand-by current consumption and also is capable of high speed amplification of a small slight potential difference generated by memory cells. This latch sense amplifier circuit is, however, disadvantageous in that any malfunction is likely to appear on the sense amplifier circuit because a flip-flop in a latch circuit performs an amplification by a slight potential difference of several tens of millivolts. In order to avoid any malfunction of the sense amplifier circuit, a sufficient margin for potential difference is needed.
FIG. 1 is a circuit diagram illustrative of a conventional latch sense amplifier circuit. The conventional latch sense amplifier circuit comprises a flip-flop 1, a transfer gate 2, a next stage buffer 3A and an output circuit 4. The flip-flop 1 performs a high speed amplification of data from memory cells up to a level defined to be a difference of a high power voltage Vcc from a ground potential GND so as to output paired complementary signals therefrom. The transfer gate 2 is connected between the flip-flop 1 and the read buses RBT and RBB, so that the transfer gate 2 disconnects the flip-flop 1 from read buses RBT and RBB for latching data from the memory cells. The next stage buffer 3A is connected to an output side of the flip-flop 1 for receiving the amplified complementary signals from the flip-flop 1. The output circuit 4 are connected to the next stage buffer 3A for receiving output from the next stage buffer 3A to output the amplified memory cell data.
The flip-flop 1 has a parallel connection of first and second inverters INV1 and INV2 between both nodes SAT and SAB. Directions of the first and second inverters INV1 and INV2 are opposite to each other to form a closed loop. Namely, an output side of the first inverter INV1 is connected to an input side of the second inverter INV2 and an output side of the second inverter INV2 is connected to an input side of the first inverter INV1. Power terminals of the first and second inverters INV1 and INV2 are supplied with a second sense amplifier activation signal SE2 If the second sense amplifier activation signal SE2 is low level or inactivated level, then the flip-flop 1 is inactivated to be inoperable. Ground terminals of the first and second inverters INV1 and INV2 are connected through an n-channel MOS field effect transistor Q1 to a ground line GND. The n-channel MOS field effect transistor Q1 has a gate receiving a first sense amplifier activation signal SE1. If the fist sense amplifier activation signal SE1 is low level, then the nodes SAT and SAB awe kept to be the high power voltage level Vcc.
The transfer gate 2 has first and second p-channel MOS field effect transistors Q2 and Q3 which have gates receiving the second sense amplifier activation signal SE2. The first p-channel MOS field effect transistor Q2 is connected in series between the read bus RBT and the node SAT. The second p-channel MOS field effect transistor Q3 is connected in series between the read bus RBB and the node SAB which are connected to the opposite sides of the closed loops. If the second sense amplifier activation signal SE2 is high level, then the flip-flop 1 is disconnected from the read buses RBT and RBB.
The next stage buffer 3A and the output circuit 4 have well known circuit configurations as disclosed in Japanese laid-open patent publications Nos. 3-41820 and 4-109494.
The next stage buffer 3A has a pair of first and second NOR gates NOR1 and NOR2. One input of each of the first and second NOR gates NOR1 and NOR2 is connected to an output side of a third inverter INV3. This third inverter INV3 has an input side receiving the first sense amplifier activation signal SE1. Namely, the inverted first sense amplifier activation signal SE1-bar is applied to one input of each of the first and second NOR gates NOR1 and NOR2. Other terminal of the first NOR gate NOR1 is connected to the node SAT. Other terminal of the second NOR gate NOR2 is connected to the node SAB.
The output circuit 4 has a fourth inverter INV4 and a series connection of a third p-channel MOS field effect transistor Q4 and a second n-channel MOS field effect transistor Q5 between a high voltage line and a ground line. The third p-channel MOS field effect transistor Q4 is connected to the high voltage line. The second n-channel MOS field effect transistor Q5 is connected to the ground line. The fourth inverter INV4 has an input side connected to an output side of the second NOR gate NOR2. The third p-channel MOS field effect transistor Q4 has a gate connected to the output of the fourth inverter INV4. The second n-channel MOS field effect transistor Q5 has a gate connected to the output of the first NOR gate NOR1. An output terminal of the latch sense amplifier cirucit is connected to an intermediate node between the third p-channel MOS field effect transistor Q4 and the second n-channel MOS field effect transistor Q5. An output signal SAOUT is outputted from the output terminal.
The following descriptions will focus on operations of the above described latch sense amplifier circuit. A memory cell is selected in data read operation. A small or slight potential difference is generated by the memory cell. This small or slight potential difference is transmitted to the sense amplifier circuit through digit lines not illustrated, read buses RBT and RBB which provide interconnections between the digit lines and the sense amplifier circuit. The small or slight potential difference is further transmitted through the transfer gate 2. The small or slight potential difference appears across the nodes SAT and SAB. Thus, the small or slight potential difference appears across the opposite sides of the closed loop of the first and second inverters INV1 and INV2.
If the first sense amplifier activation signal SE1 becomes high level, then the first n-channel MOS field effect transistor Q1 turns ON, whereby the small or slight potential difference gradually increases and also the potentials of the nodes SAT and SAB drop to an intermediate level between the high voltage level Vcc and the ground level. When a sufficient voltage for amplification is generated across the nodes SAT and SAB, the second sense amplifier activation signal SE2 becomes high level, whereby a power is supplied to the flip-flop 1 and the potential of the node SAT rises up to the high voltage level whilst the potential of the node SAB drops to the ground level. Namely, the potential difference between the nodes SAT and SAB is increased to the potential difference between the high voltage level Vcc and the ground level GND. Since the first sense amplifier activation signal SE1 has been activated in high level, both the first and second NOR gates NOR1 and NOR2 in the next stage buffer 3 are activated, so that data signals on the nodes SAT and SAB are transmitted to the output circuit 4, whereby data read from the selected memory cells are output from the output terminal as an output signal SAOUT.
FIG. 2 is a circuit diagram illustrative of each of first and second NOR gates NOR1 and NOR2 in the next stage buffer 3A in the latch sense amplifier circuit of FIG. 1. Each of the first and second NOR gates NOR1 and NOR2 in the next stage buffer has the normal circuit configuration. In this case, the following problems are raised. The NOR gate comprises two p-channel MOS field effect transistors Q6 and Q7 and two n-channel MOS field effect transistors Q8 and Q9 The two p-channel MOS field effect transistors Q6 and Q7 are connected in series between the high voltage line Vcc and an output node OUT. The two n-channel MOS field effect transistors Q8 and Q9 are connected in parallel to each other between the output node OUT and the ground line GND. Gates of the p-channel MOS field effect transistor Q6 and the n-channel MOS field effect transistor Q8 are connected to the node SAT if the NOR gate is the, fist NOR gate NOR1 or connected to the node SAB if the NOR gate is the second NOR gate NOR2. Gates of the p-channel MOS field effect transistor Q7 and the n-channel MOS field effect transistor Q9 are connected to the output side of the third inverter INV3 for receiving the inverted signal SE1-bar to the first sense amplifier activation signal SE1.
In the first NOR gate NOR1, a node between the two p-channel MOS field effect transistors Q6 and Q7 is defined to be a node 1T. In the second NOR gate NOR2, a node between the two p-channel MOS field effect transistors Q6 and Q7 is defined to be a node 1B. A potential of the node SAT is defined to be a potential Vsat. A potential of the node SAB is defined to be a potential Vsab. A potential of the node 1T is defined to be a potential V1t. A potential of the node 1B is defined to be a potential V1b. In the first NOR gate NOR1, the potential Vsat is applied to the gates of the p-channel MOS field effect transistor Q6 and the n-channel MOS field effect transistor Q8. A gate-source potential difference Vgs appears amass the gate and source of the p-channel MOS field effect transistor Q6 in the first NOR gate NOR1. This gate-source potential difference Vgs is defined to be Vsatxe2x88x92V1t. In the second NOR gate NOR2, the potential Vsab is applied to the gates of the p-channel MOS field effect transistor Q6 and the n-channel MOS field effect transistor Q8. A gate-source potential difference Vgs appears across the gate and source of the p-channel MOS field effect transistor Q6 in the second NOR gate NOR2 his gate-source potential difference Vgs is defined to be Vsabxe2x88x92V1b. 
Although the potentials of the nodes SAT and SAB has a slight difference from each other, those potentials are almost the same as each other. Namely, the potentials of the nodes SAT and SAB are independent from previous read/write operations of the sense amplifier circuit in the previous cycle. In contrast, potentials of the nodes 1T and 1B depend upon previous read/write operations of the sense amplifier circuit in the previous cycle.
It is assumed that in the previous cycle, data in high level had been outputted as the sense amplifier output SAOUT, and also that the p-channel MOS field effect transistor has a threshold voltage Vthp. Under this assumptions, if the inverted signal SE1-bar to the first sense amplifier activation signal SE1 becomes high level and the read operation is finished, then the potential of the node 1B in the second NOR gate NOR2 becomes Vcc, whilst the potential of the node 1T in the first NOR gate NOR2 becomes Vthp. After the read operation has been finished and then the odes SAT and SAB are again pre-charged at Vcc. Since the potentials of he nodes 1T and 1B are different from each other, a first coupling capacitance C1 between the nodes SAT and 1T in the first NOR gate NOR1 is different from a second coupling capacitance C2 between the nodes SAB and 1B in the second NOR gate NOR2.
In this example, the second coupling capacitance C2 generated between the nodes SAB and 1B in the second NOR gate NOR2 is small whilst the first coupling capacitance C1 between the nodes SAT and 1T in the first NOR gate NOR1 is large. A difference between the first coupling capacitance C1 and the second coupling capacitance C2 causes a potential difference between the nodes SAT and SAB to become small during the read operation. For example, data in low level are about to be outputted as the sense amplifier output SAOUT. This means that the small or slight potential difference is about to be amplified under condition of Vsat less than Vsab.
It is considered that the firs sense amplifier activation signal SE1 has been changed from the low level to the high level, the potentials of the nodes SAT and SAB are about to drop to one half of the high voltage level Vcc with keeping the small or slight difference in potential between the nodes SAT and SAB. The potential of the node 1B of the p-channel MOS field effect transistor Q6 is close to the high voltage level Vcc, for which reason a small coupling capacitance appears between the gate and source of the p-channel MOS field effect transistor Q6. The gate voltage level of the p-channel MOS field effect transistor Q6 or the potential of the node SAB is likely to be dropped. In contrast, the potential of the node 1T of the p-channel MOS field effect transistor Q6 is close to the ground level GND, for which reason a large coupling capacitance appears between the gate and source of the p-channel MOS field effect transistor Q6. The rate of drop in gate voltage level of the p-channel MOS field effect transistor Q6 or the potential of the node SAT is likely to be delayed.
Whereas the potential Vsat of the node SAT should have to be kept smaller than the potential Vsab of the node SAB, the potential Vsat of the node SAT may become almost equal to or larger than the potential Vsab of the node SAB during the potentials Vsat and Vsab dropping to one half level of the high voltage level Vcc. Otherwise, the difference between the potentials Vsat and Vsab becomes small. This makes it difficult for the latch sense amplifier circuit to perform the required correct latch operations.
The above described problems are also common to when the next stage buffer comprises a pair of NAND gates in place of the above NOR gates.
The prior art techniques for solving the problems with the operational margin of the sense amplifier are, for example, disclosed in Japanese laid-open patent publications Nos. 62-275394 and 10-11973. Japanese laid-open patent publication No 62-275394 addresses how to solve a different problem from the above described problems, for which reason the prior art technique disclosed in this Japanese publication is incapable of solving the above described problem. Japanese laid-pen patent publication No. 10-11973 addresses how to solve the problem with the parasitic capacitance between the bit lines, for which reason the prior art technique disclosed in this Japanese publication is incapable of solving the above described problem.
In the above stances, it had been required to develop a novel latch sense amplifier circuit with an enlarged latch operational margin free from the above problem.
Accordingly, it is an object of the present invention to provide a novel latch sense amplifier circuit free from the above problems.
It is a further object of the present invention to provide a novel latch sense amplifier circuit with an enlarged latch operational margin.
The present invention provides a next stage buffer receiving a pair of complementary signals from a flip-flop in a latch sense amplifier circuit. The next stage buffer comprises: a plurality of logic gates of the same type, each of which individually includes a series connection of at least an individual first conductivity type field effect transistor individually provided to the plurality of logic gates and a common first conductivity type field effect transistor commonly provided to the plurality of logic gates, and the common first conductivity type field effect transistor is connected to a carrier supply line which supplies carriers to the common first conductivity type field effect transistor, so that the plurality of logic gates have a common node between the first conductivity type field effect transistors and the common first conductivity type field effect transistor.
The provision of the common first conductivity type field effect transistor forms the common node between the first conductivity type field effect transistors and the common first conductivity type field effect transistor. This configuration causes that potentials of the sources of the individual first conductivity type field effect transistors individually provided in the plural logic gates are equal to each other, whereby no difference in the coupling noise is caused between the plural logic gates in the next stage buffer in the latch sense amplifier. The above novel configuration allows enlarged latch operation margin, and also makes the latch sense amplifier circuit free from the problems described above.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.